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E-Fuse MX5069 High-Side N_FET Driver Efficiently Manage Power Distribution For 24V And 48V Industrial Systems
| Reverse Polarity Protection: | Yes | Manufacturer: | Multiple Manufacturers |
| Overcurrent Protection: | Yes | Operating Temperature Range: | -40°C To +125°C |
| Overvoltage Protection: | Yes | Package Type: | Surface Mount |
| Short Circuit Protection: | Yes | ||
| Highlight: | MX5069 EFuse IC,48V EFuse IC,24V EFuse IC | ||
Product Description
E-Fuse MX5069 High-Side N_FET Driver Efficiently Manage Power Distribution For 24V And 48V Industrial Systems
The MX5069 high-side N_FET driver works with an external MOSFET and acts as an ideal diode rectifier when connected in series with the power supply. This controller enables MOSFETs to replace diode rectifiers in power distribution networks,reducing power loss and voltage drop. The MX5069 controller provides charge pump gate drive for an external N- channel MOSFET and fast response comparator to turnoff the FET when current flows in reverse.The current limit in the external series pass N-Channel.MOSFET are programmable. The input undervoltage and overvoltage lockout levels are programmabled by resistance divider networks. The MX5069 automatically restarts at a fixed duty cycle. MX5069 is available in 10-pin DFN3*3 and MSOP10Lpackage.
Features
♦ Wide operating range: 5V to 85V
♦ Adjustable current limit
♦ Circuit breaker function for severe overcurrent events
♦ Internal high side charge pump and gate driver for external N-channel MOSFET
♦ 50ns fast response to current reversal
♦ Adjustable undervoltage lockout (UVLO)
♦ Adjustable overvoltage lockout (OVP)
♦ Active low open drain POWER GOOD output
♦ Available with automatic restart
♦ 10-Pin DFN3*3-10L and MSOP10 package
Applications
♦ Server backplane systems
♦ Base station power distribution systems
♦ Solid state circuit breaker
♦ 24V and 48V Industrial systems
Ordering information
| Part Number | Description |
| MX5069D | DFN3*3-10L |
| MX5069MS | MSOP10L |
| MPQ | 3000pcs |
Package dissipation rating
| Package | RθJA (℃/W) |
| DFN3*3-10L | 50 |
| MSOP10 | 156 |
Absolute maximum ratings
| Parameter | Value |
| VIN to GND | -0.3 to 90V |
| SENSE, OUT to GND | -0.3 to 90V |
| GATE to GND | -0.3 to 100V |
| OUT to GND (1ms transient) | -0.3 to 95V |
| UVLO to GND | -0.3 to 90V |
| OVP, PGD to GND | -0.3 to 7V |
| VIN to SENSE | -0.3 to 0.3V |
| ILIM to GND | -0.3V to 3.5V |
| Maximum junction temperature, TJMAX | 150℃ |
| Storage temperature, Tstg | -65 to 150℃ |
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Functional operation of the device at any conditions beyond those indicated in the Recommended Operating Conditions section is not implied.
Recommended operating condition
| Symbol | Range |
| Supply voltage | 5 to 85V |
| PGD off voltage | 0 to 5V |
| ILIM voltage | 2.7V max |
| Junction temperature | -40 to 125℃ |
Terminal assignments
| PIN NO. | PIN name | Description | |
| MSOP 10 | DFN3*3 | ||
| 1 | 10 | SENSE | Current sense input: The voltage across the current sense resistor (RS) is measured from VIN to this pin. |
| 2 | 9 | VIN | Positive supply input: A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off. |
| 3 | 1 | UVLO/EN | This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass MOSFET. As an UVLOpin, it can be used to program different UVLO trip point via external resistor divider. |
| 4 | 2 | OVP | Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turnoff threshold. The disabled threshold at the pin is 1.23V. |
| 5 | 8 | GND | Circuit ground |
| 6 | 3 | SST | A capacitor from this pinto GND sets output voltage slew rate. |
| 7 | 4 | ILIM | Current limit set: An external resistor connected to this pin, combined with a current detection resistor to achieve overcurrent protection. |
| 8 | 5 | PGD | Power Good indicator: An open drain output. |
| 9 | 7 | OUT | Output feedback: Connect to the output rail (external MOSFET source). |
| 10 | 6 | GATE | Gate drive output: Connect to the external MOSFET’s gate. This pin's voltage is typically 12V above the OUT pin when enabled. |
Electrical characteristics
VIN = 12V, UVLO=2V, OVP = GND, TJ = 25°C, unless otherwise noted.
| Symbol | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
| INPUT (VIN PIN) | ||||||
| VIN | 5 | 85 | V | |||
| IQON | Supply current | Enabled: EN/UVLO = 2V | 0.50 | 0.70 | 0.9 | mA |
| IQOFF | EN/UVLO = 0V | 0.50 | 0.60 | 0.70 | mA | |
| EN/UVLO | ||||||
| UVLOR | UVLO Threshold voltage | rising | 1.57 | V | ||
| UVLOF | UVLO Threshold voltage | falling | 1.40 | V | ||
| IUVLO | UVLO leakage current | EN/UVLO = 0V | -2.6 | uA | ||
| tDUVLO | UVLO delay | Delay to GATE high | 840 | us | ||
| Delay to GATE low | 3.4 | us | ||||
| OVP PINS | ||||||
| OVPR | OVP Threshold voltage | Rising | 1.23 | V | ||
| OVPF | OVP Threshold voltage | Falling | 1.14 | V | ||
| tDOVP | OVP delay | Delay to GATE high | 13.8 | µs | ||
| Delay to GATE low | 4.4 | |||||
| IOVP | OVP bias current | 0 | 2 | µA | ||
| OUT PIN | ||||||
| IOUT-EN | OUT bias current, enabled | OUT = VIN | 10 | µA | ||
| IOUT-DIS | OUT bias current, disabled | Disabled, OUT = 0V, SENSE = VIN | 22 | |||
| GATE CONTROL (GATE PIN) | ||||||
| Source current | Normal operation | 1 | 32 | 40 | µA | |
| IGATE | Sink current | UVLO < 1.40V | 0.1 | uA | ||
| VIN to SENSE = 150mV | 2 | A | ||||
| VGATE | Gate output voltage in normal operation | GATE-OUT voltage | 8 | 10 | 14 | V |
| VSD(REV) | Reverse VSD Threshold VIN < VOUT | VIN - VOUT | -20 | -12 | -1 | mV |
| tSD(REV) | Gate turn off time for reverse | 36 | ns | |||
| CURRENT LIMIT | ||||||
| IILIM | ILIM Charge current | 20 | uA | |||
| KA | 40 | mV/mV | ||||
| SST (SST PIN) | ||||||
| ISST | SST Charging current | Normal operation | 0 | 2 | 5 | uA |
| RSST | SST Discharging resistance | 60 | 75 | 90 | Ω | |
| VSSTmax | SST max capacitor voltage | 5.2 | V | |||
| GAINSST | SST to GATE gain | 33 | V/V | |||
| PGD | ||||||
| VPGD | Output low voltage | ISINK = 2mA | 140 | 180 | mV | |
| IPGD | Off leakage current | VPGD = 5V | 0 | µA | ||
